Solution

Given number is (ABCD)₁₆.

Convert the given hexadecimal number into binary.

Divide the binary number into blocks of 3 bits each from LSB.

(ABCD)₁₆= (1010 1011 1100 1101)₂

= (1 010 101 111 001 101)₂

= (001 010 101 111 001 101)₂

= (1 2 5 7 1 5)₈

Solution

Solution

Given number is A= 1010 and it is represented in 2’s complement form.

It is a negative number because the MSB is 1.

If MSB is 1 then append four 1s on the left side of the sign bit so that the value of the given number doesn’t change.

So, the contents of R1 are 1111 1010

Solution

The Hamming distance of the code d= 2.

So, all (d-1)= 1-bit errors can be detected.

All, 1-bit errors can be corrected if distance d >2.

Solution

M₁= 10101001

Booth’s code for M1 is:

1 0 1 0 1 0 0 1 0

-1 +1 -1 +1 -1 0 +1 -1

Number of ADD and SUB operations required= 3+4= 7

Booth’s code for M2 is:

0 1 1 1 0 0 0 0 0

+1 0 0 -1 0 0 0 0

Number of ADD and SUB operations required =1+1= 2.

Solution

(EOB)₁₆ – (ABF)₁₆ = (Y)₁₆

Convert each digit into decimal and do subtraction and then convert the result back into Hexadecimal.

For example,

consider B-F = 11- 15

Barrow 10(=16 in decimal) from the next significant digit.

11+16= 27

27-15 = 12= C.

Next significant digits are 0 and B.

Because of the barrow, 0 becomes F and E becomes D.

F-B= 4

D-A= 3

(34C)₁₆=(0011 0100 1100)₂== (001 101 001 100)₂=(1514)₈.

Solution

The Register goes through a sequence of states as shown in the table below.

The state after 4 clocks is 1011.

Solution

Initial state of all the Counters is 000.

CLK 1: Counter 1 goes to state 111. Now Counter 2 and 3 update their states (to 001 and 111, respectively) because of +ve edge.

CLK 2 : Counter 1 goes to state 110.

CLK 3 : Counter 1 goes to state 101. Counter 3 updates its states because of +ve edge. New state is 110

CLK 4 : Counter 1 goes to state 100.

CLK 5 : Counter 1 goes to state 011. Counter 3 updates its states because of +ve edge. New state is 101

CLK 6 : Counter 1 goes to state 010.

CLK 7 : Counter 1 goes to state 001. Counter 3 updates its states because of +ve edge. New state is 100

CLK 8 : Counter 1 goes to state 000.

CLK 9 : Counter 1 goes to state 111. Counter 2 and 3 update their states (010 and 011, respectively)because of +ve edge.

CLK 10 : Counter 1 goes to state 110.

CLK 11 : Counter 1 goes to state 101. Counter 3 updates its states because of +ve edge. New state is 010

After 11 clock pulses the counters 2 and 3 reached the same state i.e., 010.

Solution

Solution

Frequency F= 1/T

Total delay T= 8ns + 10ns + 12ns + 10ns

= 40ns

Frequency F= 1/T

= 1/40 GHz

= 1000/40 MHz

= 25 MHz

Solution

The characteristic equation of JK flip-flop is Q_0n= JQ’₀+ K’Q₀.

Substitute J₀=K₀=Q₁ in above equation.

Q_0n= JQ’₀+ K’Q₀.

= Q₁Q’₀+ Q₁’Q₀.

= Q₀ ⊕ Q₁

Solution

(77)_x - (77)_y = (07)_z

7x + 7 - 7y -7 = 7.

7x - 7y = 7.

x=10 and y = 9 satisfies the above equation.

RHS is (07)_z. So, z can be any value greater than 7. Hence, z=8 or 9.

Solution

Solution

Solution