Arrange following in the ascending order of their performances

X.Horizontal microprogram

Y.Vertical microprogram

Z.Hardwired control unit

X<Y<Z
Z<Y<X
Y<X<Z
All have equal performance
Difficulty Level: 1
Positive Marks: 1.00
Negative Marks: 0.33
The size of the data count register of a DMA controller is 18 bits. The processor needs to transfer a file of 32,750 kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is ___
128
Difficulty Level: 1
Positive Marks: 1.00
Negative Marks: 0.00
The time to access the first word of a specific sector of a hard disk depends on rotational speed of the disk, the average seek time and the number of sectors per track. If we want to access the entire sector instead of one word (assume a sector holds about 128 words). How longer will it take to access a sector compared to one word?
128 times longer
Same amount of time
10 times longer
64 times longer
Difficulty Level: 1
Positive Marks: 1.00
Negative Marks: 0.33
Consider a disk with a rotational rate of 6000 RPM, an average seek time of 3 ms, and an average of 250 sectors per track. What is the rotational delay of this disk (in ms)?
5
10
15
3
Difficulty Level: 1
Positive Marks: 1.00
Negative Marks: 0.33
Consider the following statements:

S1: Daisy chaining is used to assign priorities in attending interrupts.

S2: When a device raises a vectored interrupt, the CPU does polling to identify the source of the interrupt.

Choose the correct option.

Only S1 is true
Only S2 is true
Both S1 and S2 are true
Both S1 and S2 are false
Difficulty Level: 1
Positive Marks: 1.00
Negative Marks: 0.33
Select the correct statement/s: [MSQ]
In polling, the CPU periodically checks the status bits to know if any device needs its attention.
During DMA, only one of the CPU or DMA controller can be bus masters at a time.
In cycle stealing mode, once DMA becomes the master of the bus it doesn’t release the bus for many cycles.
In burst mode, once DMA becomes the master of the bus it doesn’t release the bus for many cycles.
Difficulty Level: 1
Positive Marks: 2.00
Negative Marks: 0.00
Consider a system in which the bus cycle takes 80 ns. Transfer of bus control from processor to device or device to processor, takes 250 ns. One of th e IO devices has a data transfer rate of 100 KB/sec and employs DMA. Data is transferred one byte at a time.

Suppose we employ DMA in a burst mode. That is, the DMA interface gains bus mastership prior to the start of block transfer and maintains control of the bus until the whole block is transferred. How long would the device tie up with the bus when transferring a block of 128 bytes?

2.62ms
5.2ms
1.31ms
6.3 ms
Difficulty Level: 1
Positive Marks: 2.00
Negative Marks: 0.66
Consider a disk pack with 16 surfaces, 64 tracks per surface and 256 sectors per track. 512 bytes of data are stored in a bit serial manner in a sector. The capacity of the disk pack and the number of bits required to specify a particular sector in the disk are respectively:
128 MB, 27 bits
128 MB, 18 bits
512 MB, 20 bits
64GB, 28 bit
Difficulty Level: 1
Positive Marks: 2.00
Negative Marks: 0.66
A hypothetical control unit supports 5 groups of mutually exclusive control signals. The

number of bits that are required to represent control signals in horizontal microprogramming and vertical microprogramming respectively are


Groups

G1

G2

G3

G4

G5

#Control Signals

4

8

10

20

3


45, 10
16, 48
45, 16
10, 48
Difficulty Level: 1
Positive Marks: 2.00
Negative Marks: 0.66
Consider a system in which bus cycle takes 80 ns. Transfer of bus control from processor to device or device to processor, takes 150 ns. One of the IO device has data transfer rate of 100 KB/sec and employs DMA. Data are transferred one byte at a time. How long would the device tie up with the bus when transferring a block of 512 bytes assuming DMA uses cycle stealing mode?
0.279ms
0.532ms
0.821ms
0.195ms
Difficulty Level: 1
Positive Marks: 2.00
Negative Marks: 0.66
A certain moving arm disk storage with one read/write head has the following specifications: number of tracks per surface - 100, disk rotation speed 2400 RPM, track storage capacity of 32768 bits. If the average rotational latency is X msec and data transfer rate is Y bits/sec, what are the values of X and Y?
25 ms, 2.62 Mbits / sec
12.5 ms, 1.31 Mbits / sec
1.31 ms, 12.5 Mbits / sec
2.62 ms, 25 Mbits / sec
Difficulty Level: 1
Positive Marks: 2.00
Negative Marks: 0.66
Consider the microprogrammed control unit which support 256 instructions, each of which

on an average takes 8 micro operations. The system supports 12 flag conditions and 120 control signals. If vertical microprogramming control is used in the system then the total length of control word is __________ (bits/word)

22
Difficulty Level: 1
Positive Marks: 2.00
Negative Marks: 0.00
Consider a disk pack with the following specifications 20 surfaces, 256 tracks/surface, 128 sectors/track and 256 bytes/sector. In the above disk pack formatted overhead is 32 bytes/sector then what is the formatted disk space?
128 MB
256 MB
140 MB
192 MB
Difficulty Level: 1
Positive Marks: 2.00
Negative Marks: 0.66

A hard disk has 128 sectors/ track, 20 platters, each with 2 recording surfaces and 1000 cylinders. The address of a sector is given as <c,h,s> where c → cylinder number, h → surface number, s → sector number. 0th sector is addressed as <0, 0, 0>.

The address <500, 10, 84> corresponds to sector number is ?

1073374
3243274
2073374
2561364
Difficulty Level: 1
Positive Marks: 2.00
Negative Marks: 0.66

A hard disk has 128 sectors/ track, 20 platters, each with 2 recording surface and 1000 cylinders. The address of a sector is given as <c,h,s> where c → cylinder number, h → surface number, s → sector number. 0th sector is addressed as <0, 0, 0>.

What is the address of the 104353 sector?

<20,14,63>
<19,15,63>
<20,15,33>
<20,15,44>
Difficulty Level: 1
Positive Marks: 2.00
Negative Marks: 0.66