Solution

The given instruction works in the following manner:

R1 <- R1 + M[R2]

R2 <- R2 + d, where R2 is the start of an array and d is the size of an element.

So, the given instruction has auto increment addressing mode to access the next element in the array.

Solution

Cycle time in non-pipelined implementation= 20 ns

Pipeline stages = 5

Each stage takes = 4ns

With pipelined execution the cycle time is the maximum delay of all the stages, since all the stages have equal delay it is 4ns.

Speedup = CT_old / CT_new= 20 / 4 = 5

Speedup =5

Solution

In RISC computers, register-to-register arithmetic operations only are supported as they are simple and easy to implement. So, statement A is a characteristic of RISC computers.

In RISC computers only fixed-length instruction format is used. So B is not a design characteristic of RISC.

RISC computers have fewer addressing modes. So C is also true for RISC computers.

Generally on RISC one instruction is executed per clock cycle. So D is not true for RISC systems.

Solution

It is given that there are 30% branch instructions.

There are stalls in this pipeline due to branch instructions, so stall frequency = percentage of branch instructions = 30% or 0.3

No. of stall cycles due to each branch instruction = 4 clock cycles

New CPI = (1+stall frequency * stall cycles) clock cycles / instruction

⇒ (1+0.3 * 4)

⇒ 2.2 clock cycles / instruction

Solution

Each instruction has 32 bits. To support 150 instructions, opcode must contain 8-bits. Register operand1 requires 6 bits, since the total registers are 50, Register operand 2 also requires 6 bits. So, 32 - (8+6+6) = 12 bits are left over for immediate operand.

Solution

5 stage pipeline

Delays are 1, 1.4, 1.2, 3.2, 2ns

Inter stage buffer delays are 1 ns

3rd stage is capable of knowing Branch Address, so number of stall cycles = 2

30% instructions are branch instructions

Clock time= max stage delay + BUFF delay

= 3.2 + 1 = 4.2 ns

Number of clock cycles = (1 + stall Freq * stall cycles) clocks

= (1 + 0.3 * 2) clocks

= 1.6 clocks

Execution time = 1.6 * 4.2 ns / instruction

= 6.72 ns / instruction

Execution time for 1200 instructions = 6.72 ns / instruction * 1200 instruction

= 8064 ns

Solution

Follow the below timing diagram with the pipeline stages:

Between I0 and I1 there is no dependency so the OF stage of I1 happens at the same time when PO stage of I0 is going on, at time t4. And once the PO stage of I0 is completed at t4 then PO stage of I1 starts at t5.

But between I1 and I2 there is dependency so the OF stage of I2 has to wait till WO stage of I1 is over, because there is no operand forwarding. Similarly there is dependency between I2 and I3, the OF stage of I3 can start only after the WO stage of I2. So the total no. of clock cycles needed is 19.

Since the OF stage of I2 is at t7, the ID stage of I3 is also at t7 because for a given instruction to enter a particular stage the preceding instruction has to enter the next stage.

Solution

Instruction is of size 16-bits.

All possible binary combinations = 2^16

There are 64 registers, so no. of bits needed to identify a register = 6

I-type instruction has (Opcode+Register+5 bit immediate value).

There are 8 distinct I-type instructions.

All the binary combinations possible with the I-type instructions are = 8*2^6*2^5 = 2^14

R-type instructions have 2 register operands, each of them takes 6 bits.

R-type instruction has (Opcode+Register+Register).

Let x be the number of R-type instructions.

All the possible binary combinations of R-type instructions = x*2^6*2^6 = x*2^12

The sum of I-type and R-type binary combinations should be equal to 2^16, as the instruction is 16 bits long.

x*2^12 + 2^14 = 2^16

2^12 (x+4) = 2^16

x+4 = 2^4

x = 16 - 4 = 12

Solution

Solution

CPU execution time considering all cache access are hits

(CPUExTimeWithAllHits) = IC(Instruction count) * (CPU clock cycles + memory stall cycles) * clock cycle time

= IC ( 1+ 0) * clock cycle time

= IC * clock cycle time

CPU execution time considering misses in cache

(CPUExTimeWithMissRate) = IC(Instruction count) * (CPU clock cycles + memory stall cycles) * clock cycle time

= IC ( 1 + (1+0.5) * 0.04* 30) * clock cycle time

= IC * 2.8 * clock cycle time

The performance ratio = (CPUExTimeWithMissRate/ CPUExTimeWithAllHits)

= (IC * 2.8 * clock cycle time ) / IC * clock cycle time

= 2.8

Solution

SUB r1, r2, r3 require only one memory access, reading the instruction. MUL r1, r2, (r3) require two memory accesses, the first to read the instruction and the other one to read the value from memory location(s), whose address is in r3. DIV r1, r2, @(r4) three memory accesses are made in this case, the first to read the instruction, the second to get M[r4], and the third one to get M[M[r4]]. So total memory accesses required are = 1 + 2 + 3 =6.

Solution

Let us consider that variable a is stored in register R1 and variable b is stored in register R2. (a+b) is performed by adding R2 from R1 and the result is stored in R1 that means R1=R1+R2, after performing this operation R2 becomes free. Let us consider that variable c is stored in R2 because R2 is free and variable d is stored in R3. (c+d) is performed by adding R2 to R3 and the result is stored back into R2 that means R2=R2+R3,after performing this operation R3 becomes free. And variable e is stored in R3 because R3 is free. (e-(c+d)) can be performed by subtracting R2 from R3 and the result is again stored back into R2 ( since R2=R3-R2). Now R3 is free, store f into R3 and perform R2*R3 and store it into R2, R2 = R2*R3. Finally (a-b)+(e-(c+d))*f can be performed by adding R1 to the R2 and result is stored back into R1 since R1=R1+R2. Number of registers used is only 3.

Solution

Let X is the time for program on machine 1

And Y is the time for program on machine 2

Given that Y=X-20%(X)

Y ⇒ 4/5(X)

X=number of instructions * CPI1 * Tclock1

Y=number of instructions * CPI2 * Tclock2

Given that CPI2=CPI1 + 25%(CPI1)

CPI2 ⇒ 1.25(CPI1)

X/Y=5/4

(number of instructions * CPI1 * Tclock1) / ( number of instructions * CPI2 * Tclock2)=5/4

⇒ (CPI1*(1/frequency 1)) / (1.25 CPI1 * (1/frequency 2)) = 5/4

⇒ (frequency 2) / (frequency 1) = (5/4) *(1.25) ⇒ 1.5625

⇒ frequency 2=1.5625 * frequency 1

⇒ frequency 2 = 1.5625 * 2MHZ

⇒ frequency 2 = 3.125 MHZ

Solution

Given IF = 320 ps

ID = 250 ps

EX = 500 ps

MEM = 400 ps

WB = 200 ps

Number of instructions = 2

Number of clock cycles=k+(n-1)clocks

k:number of stages

n:number of instructions

Number of cycles = 5 + (2 – 1) clocks

= 6 clocks

Cycle Time = Maximum stage delay + Register delay

Since nothing is mentioned about register delay we consider it as 0.

Cycle Time = 500ps

Time required = 6 * 500 ps

= 3000 ps

Solution

In the original design,

IF = 320 ps

ID = 250 ps

EX = 500 ps

MEM = 400 ps

WB = 200 ps

Number of instructions = 2

Number of clock cycles=k+(n-1)clocks

k:number of stages

n:number of instructions

Number of cycles = 5 + (2 – 1) clocks

= 6 clocks

Cycle Time = Maximum stage delay + Register delay

Since nothing is mentioned about register delay we consider it as 0.

Cycle Time = 500ps

Time required = 6 * 500 ps

= 3000 ps

From the given pipeline the stages with higher delays will be selected to break them into 2. Here EX stage will be split into two stages, each with delay of 500/2 = 250 ps.

Similarly, MEM will be split into two stages each with delay of 400/2 = 200 ps.

Because of this the total number of stages will become 7.

Number of instructions = 2

Number of clock cycles=k+(n-1)clocks

k:number of stages = 7

n: number of instructions

New Cycle Time = Maximum stage delay = max( 320 ps, 250 ps, 250ps, 250 ps, 200 ps, 200 ps, 200 ps) = 320ps

CT_new = 7 + (2 – 1) clock cycles = 8 clock cycles

= 8 * 320 ps

= 2560 ps

Speedup = CT_old / CT_new = 3000 / 2560 = 1.17