Solution

Number of modules required=Target capacity/given capacity

=(4M*16)/(1M*4)

= 16 modules are required.

Solution

Level-1 hit rate = 0.9

Average access time = h1*t1+(1-h1)(t1+t2)

AMAT = 0.9(12)+0.1(12+150) = 27ns

Solution

For direct mapping we will require a single comparator. So the number of comparators required in fully associative cache is more compared to set associative cache.

For fully associative cache, we need to compare the tags of all blocks in parallel. So we will need as many comparators as the number of blocks in the cache. Same can be applied to k-way associative cache. We will require k comparators. So the number of comparators

Solution

Size of the cache: 32KB

Size of the block: 64 Byte = 2^6, OFFSET bits = 6

4-way set associative

Physical address: 48-bit

No. of blocks in the cache = 32KB/64 Bytes = 512

No. of sets = 512/4 = 128 = 2^7

No. of tag bits = 48 - 7 - 6 = 35

Tag directory size in bits = TAG bits * number of Cache blocks = 35*512 = 17920 bits

Solution

L1 miss rate = 1 − 0.75 = 25%

Fraction serviced from L2 ⇒ (L1 miss rate)*(L2 hit rate) ⇒ 0.25 ∗ 0.90 = 22.5%

Solution

Access time of L1 = 2

Access Time of L2 = 8

Let miss rate of L2 cache be x.

Then, miss rate of L1 cache (2 * miss rate of L2) = 2*x

miss penalty of L2 = 20 clock cycles

miss_penalty_of_L1 = Access time of L2 + (MissRate of L2 * miss penalty L2)

= 8+(x*20)

AMAT (average memory access time) = 5

AMAT = Access time of L1 + (MissRate_of_L1 * miss_penalty_of_L1)

Substituting the values in AMAT formula, we get 5 = 2+(2*x*(8+20*x))

40x^2+16x-3=0, by solving this we get x = 0.139

x = miss rate of L2 = 0.139

So, miss rate of L1 = 2*x = 0.278

Solution

Size of the cache: 64 KB

8-way set associative cache

Physical address: 32 bits

Size of the block: 256 bytes, so OFFSET needs 8 bits

No of blocks = 64 KB / 256 Bytes = 256

No of sets = 256 / 8 = 32 sets, SET number needs 5 bits

Since the total physical address is 32 bits long, no of tag bits are 19.

For K-way set associative cache, number of comparators required = K

∴ For 8-way set associative cache number of comparators = 8

Size of each comparator = number of tag bits

∴ 19 bit comparator

Solution

Physical address : 32-bit

Size of cache : 32 KB

Each cache line holds 4 words = 4 * 4 Bytes = 16 B

Block size = Cache line size = 16B

No. of blocks in the cache = 32KB / 16B = 2K = 2^11

The given memory location 3B2D6C0E can be divided into the the three parts like tag, set no and block offset as below:

From this block number (1110) is 14 ,

And the line number ( 110 1100 0000 ) is 1728.

Solution

It was given in the question that each array element occupies 2 words and each cache block is 8 words size. So there are 4 array elements in one cache block. Whenever there is a cache miss one entire cache block is loaded from the main memory into the cache. So 4 array elements are loaded into the cache at a time. When the first element A[0] is not found in the cache, then all the 4 elements A[0], A[1], A[2], A[3] are loaded into the cache. Hence when accessing A[1] there will not be a cache miss because it is already in cache. In the same manner A[2], A[3] will also be hits when accessing the first time itself.

In the given statement each element A[i] is accessed twice, once for reading and when the value of A[i]-5 is calculated then the result is stored back into A[i].

Within one cache block holding 4 elements the total memory accesses are 8 as below:

A[0]-read , A[0]-write

A[1]-read , A[1]-write

A[2]-read , A[2]-write

A[3]-read , A[3]-write

Out of these 8 accesses only A[0]-read is a miss and all the remaining 7 accesses are hits.

Hit ratio = (7 / 8)

In %, hit rate will be = 7*100 / 8 = 87.5 %

Solution

Given that cache access time is 15 ns

main memory access time is 100 ns

hit ratio is 90%

read operations are 60% that means write operations are 40%

If nothing is mentioned we have to go with the default case i.e. hierarchical memory access.

Average time required for read operation = Tavgr = h1t1 + (1-h1)(t1+t2)

= (0.9)(15) + (0.1)(15+100)

= 25ns.

In write through policy every write operation goes to main memory simultaneously, so hit rate in cache does not matter.

In write through both the cache and main memory are updated simultaneously. So we need to take max(100,15) for the write time. Hence only 100 is taken for the write operation.

Average time required for write operation = Tavgw = 100 ns.

Tavg = 0.6(25) + (0.4)(100)

= 55 ns

Solution

Let ‘X’ be the memory block number.

Block number ‘X’ mapped to [X mod 4 ] cache block

Given Reference String : 0, 8, 15, 14, 32, 12, 18, 8, 15, 48, 12, 21, 32, 18, 21

See the below diagram to have a clear idea how the memory blocks are mapped.

0, 8, 15, 14, 32, 12, 18, 8, 15 (hit), 48, 12, 21, 32, 18(hit), 21(hit)

So Number of hits = 3,

Out of 15 memory block references 3 are hits

Therefore Hit ratio = 3 * 100 / 15

= 20%

Solution

Block size is 128 bytes, so the OFFSET needs 7 bits.

32 KB cache, 2-way set associative

Number of blocks in the cache = 32KB / 128B = 256

Number of sets in the cache = 256 / 2 = 128, so the SET number needs 7 bits

Out of the 32 bits of physical address 7 bits are needed for OFFSET and 7 bits are needed for SET number. So the number of TAG bits = 32 - 7 - 7 = 32 - 14 = 18

Since there are 18 tag bits we need 18 bit comparator and it has latency of 2*18 ns.

In a set associative cache we include the delay of the comparator and the way selection MUX.

So, hit latency = 2ns + 2(18)ns = 2 + 36 = 38 ns

Solution

Solution

Cache access time = 4 ns

Hit ratio of cache=0.95

Word size is 32 bits = 4 bytes.

Cache line size = 512 bytes = 128 words

Main memory access time=25ns(time for first word)+635ns(time for remaining 127 words, 127*5=635ns) = 660 ns

Average access time = h1*t1+(1-h1)(t1+t2) = t1+(1-h1)t2

⇒ 4+(0.05)(660) = 37 ns

Solution

Main memory is 256MB in size.

Block size is 2KB, block offset = 11 bits as it is a byte addressable memory.

Cache size = 128KB

Number of blocks in the cache = 128KB/2KB = 64

It is a 2-way set associative cache, so no. of sets in the cache = 64/2 = 32 = 2^5

In the physical address we need 5 bits for the SET number.

Since in all the options we are asked about SET numbers of the given addresses, we need to find the SET number of each of the addresses.

P1 = 0x34248A4, here SET number is (0100 1) which includes the last 1 bit of 8(1000) and binary representation of 4 (0100).

P2 = 0x3548A88, here SET number is (1000 1) which includes the last 1 bits of A( 1010 ) and binary representation of 8 (1000).

P3 = 0x36A493C here SET number is (0100 1) which includes the last 1 bit of 9 (1001) and binary representation of 4 (0100).

P4 = 0x35E5680 here SET number is (0101 0) which includes the last 1 bit of 6 (0110) and binary representation of 5 (0101).

So P1, P3 are mapped to the same cache SET.